1. Field of the Invention
The present invention relates to a method of forming a via that leads to a semiconductor device. More particularly, the present invention relates to a method of forming a landed via according to the borderless design rule.
2. Description of the Related Art
Before the development of techniques for forming deep sub-micron semiconductor devices, critical dimension (CD) of devices used to be quite large. Even if there is some misalignment in carrying out photolithographic process so that the vias are slightly offset, subsequently formed contacts can still land on the desired metallic lines. Operating characteristics of the device are affected very little by the misalignment.
However, when techniques for fabricating deep sub-micron devices are employed, critical dimensions of devices shrink considerably. Very small misalignment of vias or plugs often can have considerable effect on the operating characteristics of the devices. Alignment of vias and plugs becomes critical especially when the desired dimensions of a device exceed or approach the acceptable tolerance of the fabricating equipment. Hence, the conventional method is incapable of fabricating vias or plugs that land exactly on the desired locations according to deep-submicron device specification.
Therefore, innovative techniques for forming borderless vias or plugs are required in order to fabricate deep submicron devices. In particular, the formation of interconnects between a large number of layers to form a multi-level interconnect (MLM) system depends very much on the capacity to form high-quality borderless vias or plugs.
FIG. 1 is a schematic cross-sectional view of an ideal borderless via structure, and FIG. 2 is a schematic cross-sectional view of an actual borderless via structure illustrating the effect of microloading after a metallic layer is patterned to form a metallic line.
As shown in FIG. 1, the edges of an ideal metal line 102 and its associated barrier layer 104 are almost vertical after patterning. Hence, a subsequently formed via 106 is able to land on the barrier layer 104. When a plug 108 is formed inside the via 106, the plug 108 makes contact with the barrier layer 104 without touching the metallic line 102.
As shown in FIG. 2, due to microloading in the etching operation, a rectangular metallic line 102 and barrier layer 104 profile like the one in FIG. 1 is difficult to obtain. Instead, the patterned metallic line 202 and the barrier layer 204 have a trapezoidal profile. The tapering shape of the trapezoidal structure reduces the surface area at the top of the barrier layer 204. When a borderless via 206 is formed over the barrier layer 204, a portion of the via 206 falls outside the top surface of the barrier layer 204 and the sidewall of the metallic line 202 is exposed. Subsequently, if a plug 208 is formed inside the via 206, the plug 208 not only makes contact with the barrier layer 204, but also makes contact with the metallic line 202.
In general, a titanium silicide (TiN) layer is first deposited over the interior surface of the via 206 before the formation of the plug. The titanium silicide layer is able to strengthen the adhesion of the plug 208. However, if the titanium silicide layer is formed by a nitridation procedure, gaseous nitrogen (N.sub.2) may react with the metallic material on the metallic line 202 (usually an aluminum-copper alloy) to form aluminum nitride (AlN). Consequently, resistivity of the plug 208 increases leading to electron migration and reliability problems for the devices.